Coming Soon: (Yet another) BeagleBone Display+CapTouch cape

LCD and CTP

TL;DR: This creates a cape for the BeagleBone Black using readily available replacement spare TFT Panels and a capacitive touchscreen originally found in cheap tablets.

[ You can also follow the project at Hackaday.io ]

Thanks to the economy of scale, the market of lower-end tablets is flooded with N brands available at almost throwaway prices. Here one can buy a cheap one for less than ₹3000 ($45) and get a decent 7″ screen with capacitive touch. But when it comes to the BeagleBone Black I either saw that most of touch screens available were resistive and panels with capacitive screens were out of my budget, especially when you know you could leveraging the same economy of scale build one 🙂 . I decided to take on the challenge and build a cape for the BeagleBone out of these readily available parts.

This December during my winter break at Jakarta, I shopped at Glodok and Roxy – the electronics and mobile spare part shopping hubs respectively [compare that to HQB, Shenzhen but at a smaller scale though]. What really caught my attention was 7″ TFT panels and capacitive touch digitizers in shops – the LCDs looked very close to the cheap 7″ LCD panels being sold on eBay and other places with a Realtek-based HDMI converter which I wanted to check out lately (like this).

These panels are known by the name AT070TN9x (x=0,2,3,4) and are originally manufactured by Innolux and have 50-pin connectors with a TTL interface (datasheet here). But were the panels being sold in the markets the same AT070TN92 panels, their clones or something different? I decided to find out and requested at the shops to be able take a photo of a few models of these. Got home and tried to match the pinout on the panel with the AT070TN92. Bingo. Perfect match for almost every one of them. Even though the panels have slight dimensional differences in the bezel, they have the same pin layout and should (hopefully) be the same from the inside.

Tablet LCD - back

Here you can see the one which has KR070PM7T written on it. The giveaways – Pins 1 & 2 (VLED+) shorted, 3 & 4 (VLED-) shorted. Pins 45, 49 and 50 are not connected. If you refer the datasheets, the pin definitions seem to align.

I bought two panels and mix-matched them with available capacitive touch panels to see which one fitted the screen the best. I also bought from a nearby shop the ZIF FPC connectors for the display and the touchscreen. The display one is 50 pins, 0.5mm pitch and the touch panel has 6 pins at a 0.5mm pitch. Not exactly breadboard friendly but very PCB friendly. As seen on the image at the top of the post (not this one) the LCD is sitting over the capacitive touch panel and you can see the 6-pin connections there. No reverse engineering needed for the capacitive touch FPC as the connections for the 6 pins are already highlighted in the image!

Okay, now I had to find a good driver for the LCD. I was aware of the TI TFP401 DVI (HDMI) receiver and could get samples if I wanted. But hey, the BeagleBone converts from TTL to HDMI and then I’m gonna convert HDMI to TTL, right? Why not just cut through the layers and wire the display directly? Should just be D0-D15, VSYNC, HSYNC, PCLK, 3V3, backlight, adjust LCD driver resolution, timings and done. Turns out we’re not done, yet.

The catch

Every LCD requires a high voltage to control the twist of individual liquid crystals. This voltage is usually internally generated using charge pumps but turns out that this “dirty” LCD panel ( DirtyPCBs 😛 ) expects the voltages to be supplied externally to it. The LCD expects approximately 10.4V for AVDD, 16V for VGH and -7V for VGL to be supplied to it. Hmm, how do I generate these?

The answer was not very hard to find. I was able to get Allwinner’s A13 based reference design for tablets that use a display (no points for guessing which one) with a 50 pin interface. Looking at their gate voltage generation circuits, we get this:

lcd-driving-circuit

This app note from Maxim Integrated explains what we’re looking at [scroll down to the end of the appnote]. The AVDD rail draws the maximum current so it gets powered it by the boost converter. Then the diode and the capacitors form a charge pump generating approximately +21 V and -10.4 V from that rail and the Zener regulates it down to the needed voltages. Very cool.

I’ve ordered some boost converters from AliExpress, the ones called SY7201 and XR1151 which are as of now stuck in the Chinese New Year holiday shutdown. Until then I would test with a TPS61061 which I have at hand.

The design

The schematic of a beta cape is almost done and I’m proceeding with routing of the PCB as at the time of writing. Here’s a peek on how the schematic looks right now, the final will be different from this one:

bb-disp-sch1

The beta version is to be a locally fabricated quick turnaround prototype so that I get something to work up the software side until the PCB for the first batch is manufactured. The production cape may include termination resistors or a 74LVC322245 buffer.

The capacitive touch side is simple. Two I2C pins and an interrupt pin to inform of touches. Turns out that the LCD uses only 47 out of the 50 signals and I can squeeze these three lines into the same FPC as the display using an extension cable and adapter PCB. So I’ve done it this way as can be seen above. The Linux kernel already contains a driver for the ft5x06 in drivers/input/touchscreen/edt_ft5x06.c . So getting the touch for the LCD should just be equivalent to writing some device tree code to invoke the module.

That was a long post. The next posts would feature testing of the capacitive touch panel and of the prototype.

Introducing: The BeagleLogic Cape

BeagleLogic Cape - 3D Render

After coding up the BeagleLogic project, I thought that it would be great to have an add-on cape for the project that provides buffering and also makes the inputs of the BeagleBone Black tolerant to TTL logic voltage levels (up to 5.5V) allowing BeagleLogic to debug external projects with ease. Hence introducing the BeagleLogic cape, the 3D render of which you can see above. The design is done in KiCad.

The design source and gerbers will be made available on the BeagleLogic GitHub repository after I physically assemble and verify the design.

Design & Layout

The cape design is simple enough to just have a single layer layout, as you can see in the render above the top layer is entirely a ground plane but for a single trace. Since the top isn’t much populated I added useful information on the top silkscreen including indexing the pin headers on the Bone on both sides.

The logic channels are accessed via 2×14 right angled pin headers. The upper row of headers are the actual logic channels while the bottom row is all GND pins. The pin headers are arranged in a MSB-to-LSB fashion. This means that the rightmost pin when viewed from the top is raw bit 0 of the captured logic samples. Note that sigrok will use the names of the actual Bone pins so bit 0 (Channel 1) is to be identified as P8_45, bit 1 (Ch2) is P8_46 and so on. The numbering is a little non-obvious but it’s because that’s the way the pins are arranged on the BeagleBone GPIO header. But don’t worry as the cape lists the pin ID of each logic channel so you don’t have to look it up in the pin diagrams.

One important point here. Only the first 12 channels can be used by default. To use the last two channels, you must disable eMMC first and solder 0R resistors or bridge the two resistors R8 and R9 on the bottom side to enable them. Otherwise the buffer will drive those two pins and you will damage the eMMC of the board and also void the warranty.

Here’s a shot of the schematic (click to enlarge). This is for reference only with respect to the current board and the released schematic may or may not be the same

Cape Schematic

The active buffer is a TI 74LVCH16T245 or equivalent. The buffer is powered from the VDD_3V3B power rail. The OE pin initially pulled is driven using an arrangment of a BSS138 N-MOSFET whose gate is connected to SYS_RESETn of the Bone. This should ensure that the logic input pins, which are also the system boot pins, are not driven by the buffer until the startup has completed.

This version of the design has a 0R resistor through which the VDD_3V3B powers the VDDA side rail of the 16245. If you remove the short and connect it to a 1.8V supply it should become compatible with 1.8V logic levels. I am however thinking of a better solution to the problem and should address this in the next released design.

There’s the officially required cape EEPROM on the bottom side as well, I presume this could be rendered redundant as the community moves towards the Universal Cape concept. But the footprints are there, just in case.

Manufacturing

The first prototype cape has been manufactured by DirtyPCBs.com as a 2-layer Black 10x10cm protopack. It has been shipped as of the time of writing and should reach me next week. I ordered the boards as a Rush order (48h turnaround time) and got it shipped via DHL so that I could have the boards in hand before Christmas rush. I would be using their services further if the boards work out well, looking forward to receive them!

Since I had left space on the panel, and there’s free panelizing so I managed to squeeze some more of my designs into the panel and make the best use of the available real estate. I would write more about those in the coming posts.

So that’s pretty much it. Design suggestions are welcome, and I’ll see if they can be accomodated in the subsequent hardware revisions. Once I test and it all works, the design files will be made available as I have written above.